The present invention relates to instruction decoders as are employed, for example, in microprocessors.
An instruction decoder encodes instructions into control signals and parameters for a data path. The coding depends on the status signals. The status signals depend on the state of the computer, particularly on register contents, on memory contents and on the executed instruction in each case.
In general, an instruction has the form “op, [address 1], . . . , [address k], [parameter]”. The expressions between square brackets [ ] may or may not occur, i.e. they are optional. In the following example, k=2. “op” refers to the operation to be carried out. Examples are “add”, “XOR”, “jump”. The addresses [address 1], . . . , [address 1] are register addresses of the register file, also referred to as register field.
In the instruction “add, address 1, address 2, address 3”, the data stored in the registers at the addresses “address 1” and “address 2” are added and written into the register with the address “address 3”. There is no parameter in this instruction.
The instruction decoder is responsible for transforming the instruction to a sequence of control words. In a sequence of control words associated with an instruction by the decoder, a sequence of control signals for the data path and corresponding parameters are determined so that the instruction present at the instruction decoder is executed in the computer.
In general, the sequence of control words associated with an instruction does not only depend on the instruction, but, as mentioned, also on the state of the computer and, in certain rare cases, also on the parameters of the instruction. The state of the computer affects the sequence of control signals by the status signals of the computer.
More specifically, various sequences of control signals are associated with an instruction, wherein the sequence of control signals that is actually to be used is selected by the status signals and also by the values of the parameters.
If, for example, the parameters are an address in the external memory, the value of a particular bit of this address may decide, for example, which external memory is accessed. For an instruction, the number of control words in the various sequences of control words is generally different.
To explain this in more detail, it will be assumed in the following that, in the considered processor, one sequence of control words, two different sequences of control words or three different sequences of control words are associated with an instruction.
A generalization to more than three different sequences of control words is possible.
If two different sequences of control words are associated with an instruction, they start with some common control signal words and branch depending on the values of certain status symbols or certain parameter values.
As an example, consider the instruction “if Reg(address 1)≦i goto address 2” (corresponding to a JLE address 1, i, address 2). The instruction contains the address “address 1” and the parameter “i, address 2”, which is given here by an integer value i and an address “address 2”. The operation code, which is also abbreviated as opcode, is “if Reg( )≦( ) goto( )”.
First, the contents of the register with the address “address 1” are compared to the value i. For this purpose, the contents of the register with the address “address 1” in the register field are read, the read value is subtracted from the, for example, sign-extended parameter i in the arithmetic logic unit, abbreviated ALU. After the subtraction, the instruction branches. Depending on the value, 0 or 1, of the sign bit of the ALU, the process proceeds with the next instruction or the instruction with the relative address “address 2”.
The considered instruction is thus associated with two different control sequences which branch after a common initial sequence. The status signal selecting and/or determining a control sequence from the two possible control sequences at the branch point is here the sign bit of the ALU.
In the command “addi Reg(address 1), Reg(address 2), K”, “address 1” and “address 2” are addresses of registers of the register field, and the parameter “K” is an integer number and/or an integer natural number which is added to the value stored in register 1. The sum is stored in the register of the register field with the address “address 2”. Only one control sequence is associated with this command.
If three different sequences of control words are associated with an instruction, these three sequences start with some common control words, they branch into two branches depending on the values of certain status symbols and/or status signals or certain parameter words, and one of the two branches then branches a second time depending on further status signals or parameter values.
The structure of the instruction decoder may be described as follows and/or the following three tasks may be associated with the instruction decoder: 1. determining sequences of control signal words for the data path; 2. determining sequences of control signal words for a control logic for applying the parameters of the instructions for modification to the ALU or a special sign extension unit. Such operations are, for example, sign extensions, inversion of all bits, inversion of selected bits of the parameters of the instructions. These operations may be performed in the ALU in most cases and, if any, partially in a special sign extension unit; 3. determining 1-out-of-n control signals for the register field from the binary addresses for the corresponding registers.
The first two tasks are combined in the following to form one task “determining sequences of control signals for data path and control logic”. Correspondingly, the instruction decoder may be structurally made of the two following units: 1. module for determining control signal sequences for the data path and for the control logic; 2. address decoder for the register field.
In the following, the module for determining the sequences of control signals is described in more detail. For this purpose, first consider the case that two sequences of control words are associated with an instruction, wherein the current sequence of control words is selected by a function of the status signals or parameters. A control word Wi consists of a control signal word Si=s1i, . . . , snii and a parameter word Pi=p1i, . . . , pmii.
The components s1i, . . . , snii of the control signal word Si do not depend on the parameters of the instruction, but only on the operation code (opcode) and on the status signals or the parameter values of the instruction via the selection of the sequence of control signal words. The components p1i, . . . , pmii of the parameter word Pi are determined by the parameters of the instruction. They also depend on the status signals.
The module for determining the control sequences determines the associated sequence of control signal words for a considered instruction depending on the status signals or the parameter values.
In the following, now consider, by way of example, an instruction “instruction” with which the following two sequences of control signal words are associated:    1. S1, S2, . . . , Si; Si+1, . . . , Sn     2. S1, S2, . . . , Si; Si+1; . . . , Sn′
As a specific example, consider the two sequences    1. S1, S2; S3, S4     2. S1, S2; S3′, S4′, S5′in the following, which are associated with the instruction “instruction”.
The first i, in the example i=2, control signal words S1, S2 are equal in both sequences. The first or the second sequence is selected depending on the values of certain status signals. Such an association may be realized with a read-only memory, abbreviated ROM, and a counter.
The control signal words S1, S2, . . . , Si are deposited at the consecutive addresses A+1, A+2, . . . , A+i and/or A1, A2, . . . , Ai, a mask of the status signals to be evaluated is deposited, for example, at the address A+i+1 and/or Ai+1, a vector of status signals σ1, . . . , σk is deposited at the address A+i+2 and/or Ai+2, so that the status signals causing the branching assume the value necessitated for the branching. The control signal word Si+1, S3 in the example, is deposited at the address A+i+4 and/or Ai+4. The jump address and/or address A(Si+1) for the control signal word Si+1, . . . , S3, in the example, is deposited at the address A+i+3 and/or Ai+3, and the control signal words Si+1, . . . , Sn, are deposited at the following addresses.
The control signal words Si+1, Si+2, . . . , Sn are stored at the addresses A(Si+1), A(Si+1)+1 . . . , A(Si+1)+n−1. If the comparison of the actually present status symbols with the stored status symbols shows a match, the counter is correspondingly incremented to the value A+i+4 and/or Ai+4 
If the comparison of the actually present status symbols with the stored status symbols does not show a match, the address A(Si+1) stored at the address A+i+3 and/or Ai+3 is loaded into the counter, which now successively outputs the sequence of control signal words Si, Si+1, . . . , Sn. The described implementation serves only as an example, other possibilities for implementation are also possible.
For the considered example with i=2, n=4 and n′=5, the result in the ROM is
A1S1A2S2A3mask status symbols = 1, 0, 1, 1, 0A4values status symbols = 1, —, 0, 1, —A5jump address A8A6S3A7S4A8S3′A9S4′A10S5′
The control signal words S1 and S2 are stored at the addresses A1, A2. They are common to both sequences. The mask of the status symbols relevant for the decision is given at the address A3. The mask is arbitrarily assumed to be 1,0,1,1,0 in this example. Based on this mask, there is then made a decision based on the first, third and fourth status symbols which one of the two control signal sequences is to be generated. The mask at the first, third and fourth positions therefore has the value 1. The positions with the mask value 0, here the position 2 and 5, are not taken into account in the selection.
The actual values of the status symbols are given at the following address A4, whose matching with the current status symbols decides about the continuation of the instructions.
For the considered example, 1, 0 and 1 have again been entered arbitrarily at the first, third and fourth positions.
The following is to apply to the current status symbols of the ALU in this example: If the first status symbol assumes the value 1, the third one assumes the value 0 and the fourth status symbol assumes the value 1, the address A4 is incremented by two to A6, and the control signal sequence is continued with S3, S4, which are deposited at the addresses A6, A7.
If it is not the case that the first status symbol is 1 and the third status symbol is 0 and the fourth status symbol is 1, the address A4 is incremented by 1 to A5. The jump address A(S3′)=A8 is at this address.
The control signal sequences S3′, S4′ and S5′ are stored at the addresses A8, A9, A10, and the control signal sequence is continued with S3′, S4′, S5′.
If a further division of a control signal sequence depending on status symbols is necessitated, there may analogously be provided three further addresses with a mask of the relevant status symbols, with the actual values of the relevant status symbols and a jump address in the ROM.
If the continuation of a control signal sequence depends on parameter values, a mask for the parameter values may be used instead of the mask for status symbols, and the values of the parameters may be used instead of the values of the status symbols.
A bit in the mask may decide which type of mask, i.e. mask for status symbols or mask for parameters, it is.
By using the described masks and comparison bits, the status variables and the parameters may be avoided as input variables of the ROM, and the ROM with a small address width remains relatively small.
The time for processing an instruction, however, increases with each branch by an average of two and a half cycles.
The following will briefly discuss the task of the address decoder for the register field. If addresses for registers of the register field appear in a control word, they are to be coded into a 1-out-of-n bit code word by an address decoder. The associated hardware is a normal 1-out-of-n coder.
The parameters of an instruction are often used unmodified, sign-extended, negated or negated in special bits in a control word. These modifications are done depending on the respective instruction, on the specific parameter of the instruction and on status signals. Most of these operations may be performed in the ALU, for which the instruction decoder provides the control signals. The operations “sign extension” and “padding with zeros” are performed depending on the specific processor in the ALU or in a special combinatorial circuit, for example in a sign extension unit. When modifying the parameters, the task of the instruction decoder is to apply the parameters of the instructions to the ALU or to the sign extension unit at the right time, to provide the control signals and, if necessary, masks for the ALU or the sign extension unit and to provide the control signals and addresses for storing the result in the register field.
When contemplating a typical example of a command of a command set, e.g. “Mov Rj, Rk” as an example of an Mov instruction from the Intel 80251 command set, wherein the content of register Rj is moved to register Rk, it becomes obvious that, in this case, addresses are very often used. The addresses generated in the example given point to a register field which is typically a few 100 bytes in size. Thus, the address itself is a few bits wide, e.g. 6 bits for a typical implementation of an Intel 80251 processor. These addresses may now be applied, as “one-hot”-encoded addresses and/or 1-out-of-n encoded addresses, to a memory field. The memory field may be implemented, for example, as a random access memory (RAM) or a flip-flop-based register field, also referred to as a latch-based register file. The possibility of generating a faulty result due to an interference in these addresses is high, since even one single faulty bit within the address, for example, may cause a wrong register to be addressed. This may then cause, for example, a wrong value or a wrong mask to be used for a following operation, or may cause, when writing back a result of an operation, the result to be written to a wrong address, at which it is no longer possible to fall back on the result in a subsequent processing step.